Tutorial for the MASCOTS Conference 2005:

Attendees:

Senior Architects, Processor designers, DSP engineers, Software Architects, and Modeling and Simulation Specialists

Duration:

½ day combining presentation, demonstration and interactive sessions

Presenter:

Deepak Shankar is the Founder and CEO of Mirabilis Design Inc, a systems engineering solutions provider.  Shankar has an MS in Electrical Engineering from Clemson University and MBA from University of California Berkeley.  He has over 15 years experience in electronics system design and has created 3 electronic systems engineering design and simulation tools prior to Mirabilis Design.  Mr. Shankar was the founder and member of the early management team at three different startups in the systems engineering and electronics industry. He has presented at a number of IEEE and Industry Consortium conferences in Asia, Europe and the USA.

Tutorial Title:

Designing real-time architectures using performance and power analysis through Discrete-Event modeling

Benefits: 

Attendees will understand how efficient system-level architecture modeling can increase the performance of reconfigurable, real-time software designs and validate hardware performance requirements. A baseline system performance model can be developed to allow design tradeoffs and minimize impact of design changes due to technology upgrades. 

Brief:

Next generation multi-processor, multi-core systems including FPGAs will provide significant more performance than real-time application architects are accustomed with.  At the same time, the requirements of wireless technologies and higher clock rates generate power that makes cooling a challenge.  Early system tradeoffs are especially important for systems that involve high throughput or fidelity requirements, such as real-time imaging processing, or critical power requirements for hand-held consumer devices. Performance load balancing is becoming even more critical when designing new and novel multi-core microprocessor architectures.  The trade-off between power and performance on parallel processing and multi-threading will be discussed.

Decisions such as hardware-software partitioning, multi-threading vs. parallel processing, and task partitioning require evaluating numerous architectures and making large number of trade-off decisions.  System designers must make the architectures support a variety of software implementation techniques.  The trade-offs in the cache configuration for multiple cores include question such as dedicated or shared, on-chip frame buffer or off-chip, and DMA access or DSP-direct. Additional questions t raised are the number of pipeline stages, type of communication bus between the resources (cache, DMA etc.) and the cores, speed of the logic gates and custom instruction sets per execution units. 

During this tutorial, attendees will learn

1. The various models of computation available for combining different sub-systems and engineering domains

2. The use of pre-built, parameterized libraries to rapidly construct models of the of the proposed or current complex system architecture.

3. The use of statistical models, trace information, abstraction of non-essential system specification and modeling for analysis

4. The effective use of benchmark information and trace information from existing systems for validating system models

5. How system performance models can be used for creating better program proposals and justifying decisions.

There will be a demonstration on how to simulate the performance of complex systems made up of hardware, software, and networks (wired, wireless, and transaction level) very early in the specification and design cycle.  The design methodology described starts with a mathematical functional model and rough architectural proposals.  The mathematical functions are dynamically mapped on to rough architecture to achieve optimal system operation and balanced loading. Models can be successively refined from functional and transaction level down to cycle approximate and bit true detail.